Pulnix TM-4000CL Series Manual do Utilizador descarregar pdf (Página 3)

External Sync

The TM-4000CL accepts an external sync. of standard

HD and VD at TTL level for general locking to a system

sync. and clock. The external sync. is available for 15-

frame mode. The frequency requirement is as follows:

fHD = 30.77 KHz ±0.2% (split image scanning)

fVD = 14.79 Hz ± 2%

(Internal Master clock = 80.0 MHz,

Pixel clock = 40.0 MHz)

Please contact PULNiX for TM-4000CL timing charts.

No-Delay Shutter and Read-Out-Inhibit

For multiple-camera applications such as 2D or 3D

measurement and multi-angle inspection, simultaneous

image capturing at an exact shutter timing for all cameras

is a critical requirement. The TM-4000CL’s async pulse

width control mode provides no-delay shutter as standard.

Regardless of internal pulse timing, it discharges at VINIT’s

leading edge and transfers charges at the trailing edge

of the pulse. Even though each camera runs with slightly

different H and data clock timing, image capturing is

exactly simultaneous.

The TM-4000CL also has read-out-inhibit control (ROI)

to control the vertical clock start (Async Shutter #9). When

ROI is low, V-clock is stopped and the transferred charges

remain in the vertical shift registers, which works like CCD

memory. When ROI is high, it clocks out the CCD data. This

helps a single frame grabber process multiple images in

pipeline processing (sequential process).

Connector and Pin Configurations

Digital Output Connector

Shutter Control

Manual Async

0 no shutter no shutter

(1/15) (1/15)

1 1/60 1/16,000

2 1/125 1/8,000

3 1/250 1/4,000

4 1/500 1/2,000

5 1/1,000 1/1,000

6 1/2,000 1/500

7 1/4,000 1/250

8 1/8,000 1/125

9 1/16,000 Ext. pulse width

control

12-Pin Connector

1 GND (power) 7 VD in*

2 +12V 8 STROBE

3 GND (analog) 9 HD in*

4 Video out

‡

10 RXD(RS232)*

5 GND (digital) 11 INTEG/ROI*

6 VINIT in* 12 TXD(RS232)*

VINIT (External Pulse Width Control Trigger)

No-Delay Shutter (All cameras)

ROI Control: Camera #1

ROI pulse width: Min. 1H to 1frame

Camera #1 Video

Vsync

FDV (stays low)

ROI Control: Camera #2

Camera #2 Video

Max. 1H delay

FDV (stays low, high:during enable)

Discharge

ansfer Gate

No-delay Exposure

Ext. HD

LDV

Video

(analog)

Ext. VD

FDV

Video

32.5µs

67.6 ms

1024n

276n

1n=25.0 ns

2048H

2048H (active pixels)

32H

1024 active pixels

30.77KHz

Channel A output only

Data=1024 x 2

14.79fps

DR 26-pin connector 10226-6212VC

Pin# Description I/O Pin# Description I/O

1 GND 14 GND (Shield)

2 Tx OUT 0- Out 15 Tx OUT 0+ Out

3 Tx OUT 1- Out 16 Tx OUT 1+ Out

4 Tx OUT 2- Out 17 Tx OUT 2+ Out

5 Tx CLK OUT - Out 18 Tx CLK OUT+ Out

6 Tx OUT 3- Out 19 Tx OUT 3+ Out

7 Camera Cont+ In 20 Camera Cont- In(RS-232)

8 N/C (SerTFG-) 21 N/C (SerTFG+)

9 VINIT- (ccl1-) In 22 VINIT+(ccl1+) In

10 INTEG/ROI+(ccl2+) In 23 INTEG/ROI-(ccl2-) In

11 Ext HD-(ccl3-) In 24 Ext. HD+(ccl3+) In

12 Ext VD+ (ccl4+) In 25 Ext VD- (ccl4-) In

13 GND 26 GND

Camera Link Signal Assignment to Channel Link Chip (Base Conguration)

Tx IN0 Data A0 (LSB) Tx IN14 Data B5 (B9)

Tx IN1 Data A1 Tx IN15 (C0) Data Res (B0)

Tx IN2 Data A2 Tx IN16 (C6) Data Res (B6)

Tx IN3 Data A3 Tx IN17 (C7) Data Res (B7)

Tx IN4 Data A4 Tx IN18 (C1) Data Res (B1)

Tx IN5 Data A7 (8-bit MSB) Tx IN19 (C2) Data Res (B2)

Tx IN6 Data A5 Tx IN20 (C3) Data Res (B3)

Tx IN7 Data B0 (A8) Tx IN21 (C4) Data Res (B4)

Tx IN8 Data B1 (A9) Tx IN22 (C5) Data Res (B5)

Tx IN9 Data B2 (nc) Tx IN23 Reserved

Tx IN10 Data B6 (nc) Tx IN24 LDV

Tx IN11 Data B7 (nc) Tx IN25 FDV

Tx IN12 Data B3 (nc) Tx IN26 Reserved

Tx IN13 Data B4 (B8) Tx IN27 Data A6

( ) 10-bit x 2 option, Res: Reserved

Note: CLK: data clock, LDV: Line data valid, FDV: Frame data valid, INTEG:

Integration control, VINIT: Async Trigger Input.

Camera Control is available with RS-232 version and LVDS, RS-644 control

‡

Channel “A” only *Optional

Camera Link Connector

MDR-26

Pin #1

#13

#14

#26

Rear Panel top view

1 2 3 4 5 6 7 8 ... 11 12

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